Display device and manufacturing method thereof with an improved seal between the panels

ABSTRACT

A display device is presented. The display device includes first and second panels positioned substantially parallel to each other, a liquid crystal layer disposed between the first and second panels, and a sealant attaching the the first and second panels to each other and sealing in the liquid crystal layer between the two panels. A sealant portion of at least one of the first and second panels includes a rough surface, the sealant portion contacting to the sealant upon the attaching of the two panels. The rough surface in the sealant portion allows the formation of a seal between the panels that is strong enough to be is suitable for use with a flexible substrate (e.g., a plastic substrate).

RELATED APPLICATION

The present application claims priority from Korean Patent ApplicationNo. 2005-0025953 filed on Mar. 29, 2005, the disclosure of which ishereby incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a display device and a manufacturingmethod thereof, and more particularly to a flexible liquid crystaldisplay including a plastic substrate and a manufacturing methodthereof.

(b) Description of Related Art

Of the different types of flat panel displays available in the markettoday, liquid crystal displays (LCDs) and organic light emittingdisplays (OLEDs) are the most widely used.

An LCD includes two panels provided with field-generating electrodes,such as pixel electrodes and a common electrode. The panels also includepolarizers, and a liquid crystal (LC) layer is interposed between thepanels. The LCD displays images by applying voltages to thefield-generating electrodes to generate an electric field in the LClayer. The electric field determines orientations of the LC molecules inthe LC layer and adjusts the polarization of incident light.

An organic light emitting display (OLED) is a self emissive displaydevice, which displays images by exciting an emissive organic materialto generate light. The OLED includes an anode (hole injectionelectrode), a cathode (electron injection electrode), and an organiclight emission layer interposed therebetween. When the holes and theelectrons are injected into the light emission layer, they are combinedto emit light.

Because the liquid crystal display and the organic light emittingdisplay include fragile and heavy glass substrates, they are notsuitable for portability and large scale displays.

Accordingly, a display device using a substrate made from a materialsuch as plastic that is flexible as well as light and strong hasrecently been developed.

When using a plastic substrate instead of a glass substrate, advantagesof the plastic substrate such as superior portability, stability, andlight weight compared to the glass substrate may be exploited.Furthermore, plastic substrate provides additional advantages for theLCD fabrication process, which typically involves a deposition processand a printing process for a flexible display device. For example, theflexible display using the plastic substrate may be manufactured by aroll-to-roll process rather than a general sheet unit process. The useof a roll-to-roll process allows a higher yield at a lower cost,effectively reducing the production cost.

When forming the flexible display device, the strength of the adhesivematerial holding the panels together should be good enough to preventleakage of the liquid crystal even when the display device is bent.Thus, a method of forming a stronger seal between the two panels isdesired.

SUMMARY OF THE INVENTION

In one aspect, the invention is a display device that includes first andsecond panels positioned substantially parallel to each other, a liquidcrystal layer disposed between the first and second panels, and asealant sealing attaching the first and second panels to each other andsealing in the liquid crystal layer between the first and second panels.A sealant portion of at least one of the first and second panelsincludes a rough surface, the sealant portion contacting the sealantupon the attaching of the first and second panels.

The rough surface has a roughness of 20 nm to 100 nm.

The rough surface has the contact area larger than that of a smoothsurface.The first and second panels may each include a flexiblesubstrate.

The flexible substrate may include a plastic substrate.

The flexible substrate may further include a barrier coating layer and ahard coating layer formed on multiple sides of the plastic substrate.

In another aspect, the invention is a manufacturing method of a displaydevice that includes preparing a rough surface on a first panel,depositing a sealant on one of the first panel and a second panel,attaching the first and second panels with the sealant to form anenclosed space, and injecting liquid crystal into the enclosed space toform a liquid crystal layer, wherein the sealant contacts the roughsurface of the first panel.

The rough surface has a roughness of 20 nm to 100 nm.

The rough surface has the contact area larger than that of a smoothsurface.

The rough surface of the first panel may be formed by Ar plasmatreatment.

The preparing of the rough surface on the first panel rough may includealigning a shadow mask on the first panel, the shadow mask having acut-out region corresponding to a portion on the first panel where thesealant is positioned.

The method may further include attaching the first and second panels ona first supporter and a second supporter, respectively, before preparingthe rough surface on the first panel, and detaching the first and secondsupporters from the first and second panels, respectively, after theinjection of the liquid crystal.

The first and second supporters may be made of glass.

The first and second panels may each include a flexible substrate.

The flexible substrate may include a plastic substrate.

The flexible substrate may further include a barrier coating layer and ahard coating layer formed on respective sides of the plastic substrate.

The barrier and hard coating layers may include SiO₂ and SiN_(x).

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more apparent by describingembodiments thereof in detail with reference to the accompanyingdrawings, in which:

FIG. 1 is a perspective view of an LCD according to an embodiment of thepresent invention;

FIG. 2 is a layout view of a TFT array panel for an LCD according to anembodiment of the present invention;

FIG. 3 is a sectional view of an LCD shown in FIG. 1 including the TFTarray panel and a common electrode panel taken along the line III-III′shown in FIG. 2;

FIGS. 4, 6, 8, 10, and 12 are layout views of the TFT array panel forthe LCD shown in FIGS. 2 and 3 in intermediate steps of a manufacturingmethod thereof according to an embodiment of the present invention;

FIG. 5 is a sectional view of an LCD including the TFT array panel shownin FIG. 4 taken along the line V-V′;

FIG. 7 is a sectional view of an LCD including the TFT array panel shownin FIG. 6 taken along the line VII-VII′;

FIG. 9 is a sectional view of an LCD including the TFT array panel shownin FIG. 8 taken along the line IX-IX′;

FIG. 11 is a sectional view of an LCD including the TFT array panelshown in FIG. 10 taken along the line XI-XI′;

FIG. 13 is a sectional view of an LCD including the TFT array panelshown in FIG. 12 taken along the line XIII-XIII′;

FIG. 14 is a sectional view of an LCD including the TFT array panelshown in FIG. 12 taken along the line XIII-XIII′ and illustrates thestep following the step shown in FIG. 13;

FIGS. 15 to 18 are sectional views illustrating manufacturing steps of acommon electrode panel according to an embodiment of the presentinvention; and

FIG. 19 is a sectional view of the step of combining a TFT array paneland a common electrode panel in a manufacturing method according to anembodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as limited to theembodiments set forth herein.

In the drawings, the thickness of layers and regions are exaggerated forclarity. Like numerals refer to like elements throughout. It will beunderstood that when an element such as a layer, region, or substrate isreferred to as being “on” another element, it can be directly on theother element or intervening elements may also be present. In contrast,when an element is referred to as being “directly on” another element,there are no intervening elements present.

An LCD according to an embodiment of the present invention will bedescribed in detail with reference to FIGS. 1 to 3.

FIG. 1 is a perspective view of an LCD according to an embodiment of thepresent invention, FIG. 2 is a layout view of a TFT array panel for anLCD according to an embodiment of the present invention, and FIG. 3 is asectional view of an LCD shown in FIG. 1 including the TFT array paneland a common electrode panel taken along the line III-III′ shown in FIG.2.

An LCD according to an embodiment of the present invention includes aTFT array panel 100 and a common electrode panel 200 sandwiching an LClayer 3 and held together with a sealant 310.

As shown in FIG. 3, the sealant 310 attaches the panels 100 and 200together. To achieve improved adhesion of the sealant to the panels, theurfaces where the sealant 310 contacts the panels 100 and 200 arepreferably made rough.

The LC layer 3 shown in FIG. 3 may be arranged in a vertical mode or atwisted nematic mode, or may be arranged in a mode where the LCmolecules are symmetrically bent with respect to the centers of thesurfaces of the panels 100 and 200.

First, the common electrode panel 200 will be described with referenceto FIG. 3.

Referring to FIG. 3, an upper insulating substrate 210 includes aninsulating substrate 213 made of plastic, barrier coating layers 211 pand 211 q, and hard coating layers 212 p and 212 q. A barrier coatinglayer (211 p or 211 q) and a hard coating layer (212 p and 212 q) aresequentially formed on each surface of the insulating substrate 213.

The barrier coating layers 211 p and 211 q and the hard coating layers212 p and 212 q are made of SiO₂ and SiN_(x), and play a role inpreventing oxygen or moisture from penetrating into the upper substrate210. Thus, the barrier coating layers 211 p, 211 q and the hard coatinglayers 212 p, 212 q help maintain the characteristics of the commonelectrode panel 200.

The insulating substrate 213 is made of a material selected frompolyacrylate, polyethylene-terephthalate, polyethylene-naphthalate,polycarbonate, polyarylate, polyether-imide, polyethersulfone, andpolyimides.

A light blocking member 220, which is often called a black matrix forpreventing light leakage between pluralities of pixels, is formed on theupper insulating substrate 210. The light blocking member 220 mayinclude a plurality of openings that face the pixels.

A plurality of color filters 230 are formed on the upper substrate 210and they are disposed substantially in the areas enclosed by the lightblocking member 220. The color filters 230 may extend along the pixelcolumn. The color filters 230 may represent one of the primary colorssuch as red, green, and blue. The light blocking member 220 is formed bydepositing the upper surface of an upper insulating substrate 210 withan opaque material having good light-blocking characteristic such asoxidized steel, carbon black, and Cr, Ni, Fe, or a metallic oxidethereof, and patterning the deposited material through photolithographyusing a photomask.

An overcoat 250 for preventing the color filters 230 from being exposedand for providing a flat surface is formed on the color filters 230 andthe light blocking member 220. A common electrode 270, preferably madeof a transparent conductive material such as ITO and IZO, is formed onthe overcoat 250, and an alignment layer 21 is coated on the commonelectrode 270.

The surface of the sealant 310 extends from the overcoat 250 to theinsulating substrate 213 through the barrier coating layer 211 p. Thesealant 310 is formed on portions of the common electrode panel 200 in asawtooth shape, as shown in FIG. 3.

Next, the TFT array panel 100 is described in detail with reference toFIGS. 1 to 3.

The TFT array panel 100 includes a display area DA and a periphery areaPA surrounding the display area DA. The sealant 310 is positioned justoutside the boundary of the display area DA, on the periphery area PA.

A lower insulating substrate 110 includes an insulating substrate 113made of plastic, barrier coating layers 111 p and 111 q, and hardcoating layers 112 p and 112 q. A barrier coating layer (111 p or 111 q)and a hard coating layer (112 p and 112 q) are sequentially formed oneach surface of the insulating substrate 113.

A plurality of gate lines 121 are formed on the insulating substrate110.

The gate lines 121 transmit gate signals and extend substantially in atransverse direction. Each of the gate lines 121 includes a plurality ofgate electrodes 124, projections 127 projecting downward, and an endportion 129 having a large area for contact with another layer or anexternal driving circuit. A gate driving circuit (not shown) forgenerating the gate signals may be mounted on a flexible printed circuit(FPC) film (not shown), which may be attached to the substrate 110,directly mounted on the substrate 110, or integrated onto the substrate110. The gate lines 121 may extend to be connected to a driving circuitthat may be integrated on the substrate 110.

The gate lines 121 are preferably made of an Al-containing metal such asAl and an Al alloy, an Ag-containing metal such as Ag and an Ag alloy, aCu-containing metal such as Cu and a Cu alloy, a Mo-containing metalsuch as Mo and a Mo alloy, Cr, Ta, or Ti. In some embodiments, the gatelines 121 may have a multi-layered structure including two conductivefilms (not shown) having different physical characteristics. In theseembodiments, one of the two films is preferably made of alow-resistivity metal including an Al-containing metal, an Ag-containingmetal, or a Cu-containing metal for reducing signal delay or voltagedrop. The other film is preferably made of a material such as aMo-containing metal, Cr, Ta, or Ti, which has good physical, chemical,and electrical contact characteristics with other materials such asindium tin oxide (ITO) or indium zinc oxide (IZO). Examples of thesemulti-layered structure include a lower Cr film in combination with anupper Al (alloy) film and a lower Al (alloy) film in combination with anupper Mo (alloy) film. However, the gate lines 121 may be made ofvarious metals or conductors other than the ones explicitly mentionedabove.

The edges of the gate lines 121 are inclined relative to a surface ofthe substrate 110 to form an inclination angle of about 30-80 degrees.

A gate insulating layer 140, preferably made of silicon nitride (SiNx)or silicon oxide (SiOx), is formed on the gate lines 121.

A plurality of semiconductor stripes 151 preferably made of hydrogenatedamorphous silicon (abbreviated to “a-Si”) or polysilicon are formed onthe gate insulating layer 140. Each of the semiconductor stripes 151extends substantially in the longitudinal direction with respect to FIG.6 and becomes wide near the gate lines 121 such that the semiconductorstripes 151 cover large areas of the gate lines. Each of thesemiconductor stripes 151 includes a plurality of projections 154projecting toward the gate electrodes 124.

A plurality of ohmic contact stripes and islands 161 and 165 are formedon the semiconductor stripes 151. The ohmic contact stripes and islands161 and 165 are preferably made of n+hydrogenated a-Si heavily dopedwith N-type impurities such as phosphorus, or they may be made of asilicide. Each ohmic contact stripe 161 includes a plurality ofprojections 163, and the projections 163 and the ohmic contact islands165 are located in pairs on the projections 154 of the semiconductorstripes 151.

The edges of the semiconductor stripes 151 and the ohmic contacts 161and 165 are inclined relative to the surface of the substrate 110 toform inclination angles that are preferably in a range of about 30-80degrees.

A plurality of data lines 171, a plurality of drain electrodes 175, anda plurality of storage capacitor conductors 177 are formed on the ohmiccontacts 161 and 165 and the gate insulating layer 140.

The data lines 171 transmit data signals and extend substantially in thelongitudinal direction with respect to FIG. 2 to intersect the gatelines 121. Each data line 171 includes a plurality of source electrodes173 projecting toward the gate electrodes 124, and an end portion 179having a large area for contact with another layer or an externaldriving circuit. A data driving circuit (not shown) for generating thedata signals may be mounted on an FPC film (not shown), which may beattached to the substrate 110, directly mounted on the substrate 110, orintegrated onto the substrate 110. The data lines 171 may extend to beconnected to a driving circuit that may be integrated on the substrate110.

As shown in FIG. 3, the drain electrodes 175 are separated from the datalines 171 and disposed across one of the gate electrodes 124 from thesource electrodes 173.

A gate electrode 124, a source electrode 173, and a drain electrode 175along with a projection 154 of a semiconductor stripe 151 form a TFThaving a channel formed in the projection 154 disposed between thesource electrode 173 and the drain electrode 175.

The storage capacitor conductors 177 overlap the projections 127 of thegate lines 121.

The data lines 171, the drain electrodes 175, and the storage capacitorconductors 177 are preferably made of a refractory metal such as Cr, Mo,Ta, Ti, or alloys thereof. However, they may have a multilayeredstructure including a refractory metal film (not shown) and alow-resistivity film (not shown). Examples of the multi-layeredstructure are a double-layered structure including a lower Cr/Mo (alloy)film and an upper Al (alloy) film and a triple-layered structure of alower Mo (alloy) film, an intermediate Al (alloy) film, and an upper Mo(alloy) film. However, the data lines 171, the drain electrodes 175, andthe storage capacitor conductors 177 may be made of various metals orconductors.

The data lines 171, the drain electrodes 175, and the storage capacitorconductors 177 have inclined edges that form inclination angles of about30-80 degrees with respect to the surface of the gate insulating layer140.

The ohmic contacts 161 and 165 are interposed only between theunderlying semiconductor stripes 151 and the overlying conductors suchas the data lines 171 and the drain electrodes 175, and reduce thecontact resistance between the semiconductor stripes 151 and theconductors. Although the semiconductor stripes 151 are narrower than thedata lines 171 at most places, the width of the semiconductor stripes151 becomes large near the gate lines 121 as described above, to smooththe profile of the surface and thereby prevent disconnection of the datalines 171 from the semiconductor stripes 151.

As shown in FIG. 3, a passivation layer 180 is formed on the data lines171, the drain electrodes 175, the storage capacitor conductors 177, andthe exposed portions of the semiconductor stripes 151. The passivationlayer 180 includes a lower passivation film 180 p preferably made of aninorganic insulator such as silicon nitride or silicon oxide and anupper passivation film 180 q preferably made of an organic insulator.The organic insulator preferably has a dielectric constant of less thanabout 4.0, and it may have photosensitivity and may provide a flatsurface. The passivation layer 180 may have a single-layer structurepreferably made of an inorganic or organic insulator.

The passivation layer 180 has a plurality of contact holes 182, 185, and187 exposing the end portions 179 of the data lines 171, the drainelectrodes 175, and the storage capacitor conductors 177, respectively.In addition, the passivation layer 180 and the gate insulating layer 140have a plurality of contact holes 181 exposing the end portions 129 ofthe gate lines 121.

A plurality of pixel electrodes 190 and a plurality of contactassistants 81 and 82 are formed on the passivation layer 180. They arepreferably made of a transparent conductor such as ITO or IZO, or areflective conductor such as Ag, Al, Cr, or alloys thereof.

The pixel electrodes 190 are physically and electrically connected tothe drain electrodes 175 through the contact holes 185 and to thestorage capacitor conductors 177 through the contact holes 187 such thatthe pixel electrodes 190 receive data voltages from the drain electrodes175. The pixel electrodes 190 supplied with the data voltages generateelectric fields in cooperation with the common electrode 270 of thecommon electrode panel 200 supplied with a common voltage, whichdetermine the orientations of LC molecules (not shown) of an LC layer 3disposed between the two electrodes 190 and 270.

A pixel electrode 190 and the common electrode 270 form a capacitorreferred to as a “liquid crystal capacitor,” which stores appliedvoltages after the TFT turns off. An additional capacitor called a“storage capacitor,” which is connected in parallel to the liquidcrystal capacitor, is provided for enhancing the voltage storingcapacity. The storage capacitors are implemented by overlapping thepixel electrodes 190 with the gate lines 121 adjacent thereto (called“previous gate lines”). The capacitances of the storage capacitors,i.e., the storage capacitances, are increased by providing theprojections 127 at the gate lines 121 for increasing overlapping areasand by providing the storage capacitor conductors 177, which areconnected to the pixel electrodes 190 and overlap the projections 127,under the pixel electrodes 190 for decreasing the distance between theterminals.

The pixel electrodes 190 overlap the gate lines 121 and the data lines171 to increase the aperture ratio, but this is optional.

Each pixel electrode 190 may have a plurality of cutouts to change theorientations of the LC molecules.

In addition, each pixel electrode 190 may be divided into two or moresub-pixel electrodes (not shown). The sub-pixel electrodes may becapacitively coupled to each other through a coupling electrode (notshown), or connected to separate transistors (not shown).

The contact assistants 81 and 82 are connected to the end portions 129of the gate lines 121 and the end portions 179 of the data lines 171through the contact holes 181 and 182, respectively. The contactassistants 81 and 82 respectively protect the end portions 129 and 179and enhance the adhesion between the end portions 129 and 179 andexternal devices.

An alignment layer 11 is formed on the pixel electrodes 190, contactassistants 81 and 82, and the passivation layer 180.

The surface of the sealant 310 is formed in a sawtooth pattern thatextends from the upper passivation layer 180 q to the insulatingsubstrate 113. The sawtooth pattern extends through the barrier coatinglayer 111 q.

A method of manufacturing the TFT array panel shown in FIGS. 1 to 3according to an embodiment of the present invention will be nowdescribed in detail with reference to FIGS. 4 to 14.

FIGS. 4, 6, 8, 10, and 12 are layout views of the TFT array panel forthe LCD shown in FIGS. 2 and 3 in intermediate steps of a manufacturingmethod thereof according to an embodiment of the present invention, FIG.5 is a sectional view of an LCD including the TFT array panel shown inFIG. 4 taken along the line V-V′, FIG. 7 is a sectional view of an LCDincluding the TFT array panel shown in FIG. 6 taken along the lineVII-VII′, FIG. 9 is a sectional view of an LCD including the TFT arraypanel shown in FIG. 8 taken along the line IX-IX′, FIG. 11 is asectional view of an LCD including the TFT array panel shown in FIG. 10taken along the line XI-XI′, FIG. 13 is a sectional view of an LCDincluding the TFT array panel shown in FIG. 12 taken along the lineXIII-XIII′, and FIG. 14 is a sectional view of an LCD including the TFTarray panel shown in FIG. 12 taken along the line XIII-XIII′ andillustrates the step following the step shown in FIG. 13.

First, as shown in FIGS. 4 and 5, a lower insulating substrate 110 (suchas a plastic substrate) is provided.

Next, one surface of a double-sided adhesive tape 50 made of a polyimidematerial is adhered on one surface of the lower insulating substrate110, and the other surface of the adhesion tape 50 is adhered on onesurface of a supporter 40 made of a transparent material such as glassto complete the combination of the lower insulating substrate 110 andthe supporter 40.

As shown in FIGS. 4 and 5, a metal film is sputtered and patterned byphoto-etching with a photoresist pattern on the lower insulatingsubstrate 110 to form a plurality of gate lines 121 including aplurality of gate electrodes 124 and a plurality of projections 127.

Referring to FIGS. 6 and 7, after sequential deposition of a gateinsulating layer 140, an intrinsic a-Si layer, and an extrinsic a-Silayer, the extrinsic a-Si layer and the intrinsic a-Si layer arephoto-etched to form a plurality of extrinsic semiconductor stripes 164and a plurality of intrinsic semiconductor stripes 151 including aplurality of projections 154 on the gate insulating layer 140.

Referring to FIGS. 8 and 9, a metal film is sputtered and etched using aphotoresist to form a plurality of data lines 171 including a pluralityof source electrodes 173, a plurality of drain electrodes 175, and aplurality of storage capacitor conductors 177.

Before or after removing the photoresist, portions of the extrinsicsemiconductor stripes 164 that are not covered with the data lines 171,the drain electrodes 175, and the storage capacitor conductors 177 areremoved by etching to complete a plurality of ohmic contact stripes 161including a plurality of projections 163 and a plurality of ohmiccontact islands 165 and to expose portions of the intrinsicsemiconductor stripes 151. Oxygen plasma treatment may follow thereafterin order to stabilize the exposed surfaces of the semiconductor stripes151.

Referring to FIGS. 10 and 11, a lower passivation layer 180 p preferablymade of an inorganic material such as silicon nitride or silicon oxideis formed by plasma enhanced chemical vapor deposition (PECVD), and anupper passivation layer 180 q preferably made of photosensitive organicmaterial is coated on the lower passivation layer 180 p. Then, the upperpassivation layer 180 q is exposed to light through a photo mask anddeveloped to expose the portion of the lower passivation layer 180 p,and the exposed portion of the lower passivation layer 180 p is dryetched along with the gate insulating layer 140 to form a plurality ofcontact holes 181, 182, 185, and 187.

Referring to FIGS. 12 and 13, a conductive layer preferably made of atransparent material such as ITO and IZO is deposited by sputtering andis etched using the photoresist to form a plurality of pixel electrodes190 and a plurality of contact assistants 81 and 82. Sequentially, analignment layer 11 is formed on the pixel electrodes 190 and the upperpassivation layer 180 q.

Next, referring to FIG. 14, a shadow mask 60 is aligned on the TFT arraypanel 100 manufactured by the processes of FIGS. 4 to 13. As shown inFIG. 1, portions of the shadow mask 60 corresponding to portions onwhich the sealant 310 surrounds the display area DA are formed are cutout. A surface of the lower substrate 110 becomes rough by Ar plasmatreatment using the shadow mask 60. At this time, a surface roughness ofthe lower substrate 110 is about 20 nm to 100 nm.

The rough surface treatment of the lower substrate 110 may beaccomplished by any suitable known physical or chemical treatments.

Now, a method of manufacturing the common electrode panel for theflexible LCD shown in FIGS. 1 to 3 will be described with reference toFIGS. 15-19.

FIGS. 15 to 18 are sectional views illustrating manufacturing steps of acommon electrode panel according to an embodiment of the presentinvention, and FIG. 19 is a sectional view of the step of combining aTFT array panel and a common electrode panel in a manufacturing methodaccording to an embodiment of the present invention.

First, as shown in FIG. 15, an upper insulating substrate 210 made of amaterial such as plastic is provided.

Next, one surface of a double-sided adhesive tape 90 made of a polyimidematerial is adhered to one surface of the upper insulating substrate210, and the other surface of the adhesive tape 90 is adhered to onesurface of a supporter 80 made of a transparent material such as glass,to complete the combination of the upper insulating substrate 210 andthe supporter 80.

A light blocking member 220 is formed by deposition on the upper surfaceof the upper insulating substrate 210.

Referring to FIG. 16, the color filters 230 are formed on the upperinsulating substrate 210. The color filters 230 of red, green, and bluecolors are separated from each other and their edge portions extend overthe edges of the light blocking member 220.

Referring to FIG. 17, an overcoat 250 preferably made of an acrylmaterial is formed on the color filters 230 and the light blockingmember 220 to enhance the step coverage characteristics of the overlyinglayer and the flatness of the surface of the common electrode panel 200.

Subsequently, an ITO or IZO layer is deposited on the overcoat 250 toform a common electrode 270, and an alignment layer 21 is coated thereonto form the common electrode panel 200.

Next, referring to FIG. 18, a shadow mask 60 is aligned on the commonelectrode panel 200 manufactured by the processes of FIGS. 15 to 17. Asurface of the upper substrate 210 becomes rough by Ar plasma treatmentusing the shadow mask 60 to form the common electrode 270. At this time,a surface roughness of the upper substrate 210 is about 20 nm to 100 nm.The rough surface treatment of the upper substrate 210 may beaccomplished by any suitable physical or chemical treatments. Referringto FIG. 19, the TFT array panel 100 and the common electrode panel 200are attached toe ach other by the sealant 310.

The sealant 310 is formed on the rough portions of the surface of thepanels 100 and 200. The rough portions increase the contact area betweenthe panels 100, 200 and the sealant 310 to improve the strength of theseal.

LC is injected between the panels 100 and 200 to form an LC layer 3.

A hot press process is executed at about 150° C. During this process,the lower and upper substrates 100 and 200 made of plastic are supportedby the supporters 40 and 50 made of glass to prevent expansion orbending of the substrates 100 and 200.

Next, the supports 40 and 80 are removed from the TFT array panel 100and the common electrode panel 200 of the LCD by reducing the adhesivestrength of the adhesive tapes 50 and 90. of the adhesive strength ofthe adhesive tapes 50, 90 may be adjusted by controlling thetemperature, using a solvent, or irradiating ultraviolet rays, etc. Ifthe temperature is adjusted, the adhesive strength of the adhesion tapes50 and 90 becomes sufficiently weak at a temperature of less than 0degrees, allowing the supporters 40 and 80 to be removed from the TFTarray panel 100 and the common electrode panel 200 to form the LCD asshown in FIG. 3.

Because the contact surfaces of the lower and upper insulatingsubstrates and the sealant has the roughness of about 20 nm to 100 nmthrough the physical or chemical treatments, the contact area of thesealant with respect to the lower and upper insulating substratesbecomes larger. Therefore, a better seal is achieved than if there wereno rought surface, and the reliability of the LCD are improved. Althoughpreferred embodiments of the present invention have been described indetail hereinabove, it should be clearly understood that many variationsand/or modifications of the basic inventive concepts herein taught whichmay appear to those skilled in the present art will still fall withinthe spirit and scope of the present invention, as defined in theappended claims.

1. A I display device comprising: first and second panels positionedsubstantially parallel to each other; a liquid crystal layer disposedbetween the first and second panels; and a sealant attaching the firstand second panels to each other and sealing in the liquid crystal layerbetween the first and second panels, wherein a sealant portion of atleast one of the first and second panels includes a rough surface, thesealant portion contacting the sealant upon the attaching of the firstand second panels.
 2. The device of claim 1, wherein the rough surfacehas a roughness of 20 nm to 100 nm.
 3. The device of claim 2, whereinthe rough surface has the contact area larger than that of a smoothsurface.
 4. The device of claim 1, wherein the first and second panelseach includes a flexible substrate.
 5. The device of claim 4, whereinthe flexible substrate includes a plastic substrate.
 6. The device ofclaim 5, wherein the flexible substrate further includes a barriercoating layer and a hard coating layer formed on multiple sides of theplastic substrate.
 7. A manufacturing method of a display device,comprising: preparing a rough surface on a first panel; depositing asealant on one of the first panel and a second panel; attaching thefirst panel to the second panel by the sealant to form an enclosedspace; and injecting liquid crystal into the enclosed space to form aliquid crystal layer, wherein the sealant contacts the rough surface ofthe first panel.
 8. The device of claim 7, wherein the rough surface hasa roughness of 20 nm to 100 nm.
 9. The device of claim 8, wherein therough surface has the contact area larger than that of a smooth surface.10. The method of claim 7, wherein the rough surface of the first panelis formed by Ar plasma treatment.
 11. The method of claim 7, wherein thepreparing of the rough surface comprises: aligning a shadow mask on thefirst panel, the shadow mask having a cut-out region corresponding to aportion on the first panel where the sealant is positioned; and treatinga surface of the first panel using the shadow mask.
 12. The method ofclaim 11, further comprising: attaching the first and second panel on afirst supporter and a second supporter, respectively, before thepreparing of the rough surface on the first panel and detaching thefirst and second supporters from the first and second panels,respectively, after the injection of the liquid crystal.
 13. The methodof claim 12, wherein the first and second supporters are made of glass.14. The method of claim 7, wherein the first and second panels eachinclude a flexible substrate.
 15. The method of claim 14, wherein theflexible substrate includes a plastic substrate.
 16. The method of claim15, wherein the flexible substrate further includes a barrier coatinglayer and a hard coating layer formed on multiple sides of the plasticsubstrate.
 17. The method of claim 15, wherein the barrier and hardcoating layers include SiO₂ and SiN_(x).